A system-on-chip (SoC) includes various circuits. Each circuit can operate in one or modes, for example a functional mode and a power saving mode. The power saving mode can also be referred to as a clock gating mode. While clock gating is a useful method in reducing the active power of the circuit to minimal level, the method has fundamental reliability limitations that need to be addressed.
An example of an existing clock tree 100 is illustrated in FIG. 1 (prior art). The clock tree 100 includes a plurality of blocks, for example a block 105A and a block 105N. Each block includes a plurality of inverter cells. The plurality of inverter cells may also be referred to as a plurality of clock tree elements of the clock tree 100. For example, the block 105A includes a positive metal oxide semiconductor (PMOS) transistor 110A and a negative metal oxide semiconductor (NMOS) transistor 115A defining a first inverter cell. A PMOS transistor 110B and an NMOS transistor 115B define a second inverter cell. The PMOS transistor 110A and the PMOS transistor 110B enables functioning of the clock tree 100. During gating, the clock tree 100 receives a gating signal at a node 120. However, when the gating signal is at logic level LO then at least one PMOS transistor of each block is active. For example, when the gating signal is at logic level LO (falling edge) then the PMOS transistor 110A is active and hence is subject to Negative Bias Temperature Instability (NBTI) effect. The NBTI effect degrades the PMOS transistor 110A and reduces timing performance of the PMOS transistor 110A. In a similar way, at least one PMOS transistor, for example the PMOS transistor 110B, of each block is active and gets degraded when the gating signal is at logic level HI (rising edge). Also, at least one NMOS transistor, for example the NMOS transistor 115A, that is active when the gating signal is at logic level HI can get degraded due to a positive bias temperature instability (PBTI) effect. Degrading of PMOS transistors during falling edge and rising edge of the gating signal leads to asymmetric aging of the PMOS transistors. Hence, the clock tree 100 is prone to asymmetric aging of the PMOS transistors which in turn may further lead to functional failures of the clock tree 100 and other circuits on the SoC by generating delays.